Design Verification with E

by Palnitkar, Samir
4.7 out of 5 Customer Rating
ISBN: 9780131413092
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Overview

An improvement upon Verilog and VHDL, e gives engineers the speed and efficiency to improve the quality of design verification. The text offers examples and exercises as well as a fully functional demo.
  • Format: Trade Paperback
  • Author: Palnitkar, Samir
  • ISBN: 9780131413092
  • Condition: Used
  • Dimensions: 9.50 x 1.18
  • Number Of Pages: 416
  • Publication Year: 2003

Customer Reviews